1. Field of the Invention
The present invention relates to RC calibration circuits and, more particularly, to a RC calibration circuit that significantly reduces design complexity and provides greater accuracy while consuming significantly less power.
2. Description of the Related Art
On chip resistors and capacitors are commonly used in modern integrated circuits to control the frequency of poles and zeros. Often times, however, resistors can vary in value from 30 to over 100% due to variations in process, voltage, and temperature, while capacitors can vary in value from 10 to 30%. With these huge variations in values, it is difficult to tightly control the locations of the poles and zeros.
One way of compensating for these huge variations is to use a variable capacitor which is controlled by an RC calibration loop. The calibration loop simply adjusts the capacitance C of the variable capacitor, thereby adjusting the value of the RC time constant, until the location of the resulting pole or zero is placed in a desired location.
FIG. 1 shows a block diagram that illustrates a conventional RC calibration circuit 100. As shown in FIG. 1, circuit 100 includes a resistor 110 and a variable capacitor 112 that are connected in parallel between a node N and ground. In addition, a current source 114 sources a current I.sub.N into node N. A voltage V.sub.N, in turn, is defined across resistor 110 and capacitor 112.
Resistor 110, which has a resistance R.sub.N, is typically implemented as a polysilicon resistor. Variable capacitor 112, which has a capacitance C.sub.N, is typically implemented as a capacitor digital-to-analog converter (DAC). The capacitor DAC receives a digital control word DCW, and then sets the capacitance CN to a value that is defined by the control word DCW.
As further shown in FIG. 1, circuit 100 additionally includes a switch 120 which is connected between node N and ground, and an analog comparator 122 which has a first input connected to node N, a second input connected to a reference voltage V.sub.REF, and an output. Comparator 122 outputs a comparison signal CMP with a first logic state when the voltage V.sub.N is less than the reference voltage V.sub.REF, and a second logic state when the voltage V.sub.N is greater than the reference voltage V.sub.REF.
Circuit 100 also includes a counter 124 which is connected to receive a clock signal CLK from a clock source, and the compare signal CMP from comparator 122. Counter 124 is also connected to receive a switch pulse SW, and to output a count CT. Further, circuit 100 includes a control logic block 126 which outputs the control word DCW to capacitor 112, and the switch pulse SW to switch 120 and counter 124. In addition, logic block 126 receives the comparison signal CMP from comparator 122, and the count CT from counter 124.
FIGS. 2A-2C show timing diagrams that illustrate the operation of circuit 100. Prior to operation, which begins at time t.sub.0, switch 120 is closed. As a result, the voltage V.sub.N is equal to ground. When operation begins at time t.sub.0, logic block 126 outputs the switch pulse SW. In response to the rising edge of the switch pulse SW, switch 120 opens, and counter 124 begins counting the rising edges of the clock signal CLK.
At the same time, as shown in FIGS. 2A-2C, the voltage V.sub.N, which is across resistor 110 and capacitor 112, and on the first input of comparator 122, rises exponentially as described by the following equation: EQU V.sub.N =Vo(1-e.sup.t/.tau.), EQ. 1
where Vo represents the maximum voltage across capacitor 112, t represents the elapsed time, and .tau. represents the RC time constant (which is the product of the RC values of resistor 110 and capacitor 112).
When the voltage V.sub.N exceeds the reference voltage V.sub.REF, comparator 122 changes the logic state of the compare signal CMP. In response, counter 124 stops counting, and logic block 126 captures the count CT held by counter 124. After logic block 126 has captured the count CT, the falling edge of the switch pulse SW causes switch 120 to close, and counter 124 to be reset to zero. When switch 120 closes, the voltage V.sub.N discharges back to ground. Once back to ground, circuit 100 is ready to begin another comparison with the next rising edge of the switch signal SW.
The count CT captured from counter 124 is an accurate measure of the time t that elapsed from time to to time t.sub.CMPO, the time at which the voltage V.sub.N first exceeded the reference voltage V.sub.REF. Since the voltage V.sub.N is equal to the reference voltage V.sub.REF at time t.sub.cMPo (within one least significant bit of the count), and the time t is equal to t.sub.CMPO-to, logic block 126 can solve EQ. 1 for the time constant .tau..
If the time constant .tau. is less than a predetermined time constant that corresponds with the desired location of a pole, logic block 126 updates the control word DCW to increase the capacitance C.sub.N, and then outputs the updated control word DCW to capacitor 112. On the other hand, if the time constant .tau. is greater than the predetermined time constant, logic block 126 updates the control word DCW to decrease the capacitance C.sub.N, and then outputs the updated control word DCW to capacitor 112.
This process is then repeated to servo the capacitance C.sub.N of capacitor 112, and thereby the RC time constant .tau., to the value of the predetermined time constant. For example, in the first period, if the time constant .tau., which is solved for using the count CT to define the time t.sub.CMP0- t.sub.0, is less than the predetermined time constant, the control word DCW is increased to increase the capacitance C.sub.N. In the second period, if the time constant .tau., which is solved for using the count CT to define the time t.sub.CMP1- t.sub.1, is again less than the predetermined time constant, although greater than the previous time constant, the control word DCW is again increased to further increase the capacitance C.sub.N.
In the third period, if the time constant .tau., which is solved for using the count CT to define the time t.sub.CMP2- t.sub.2, is now greater than the predetermined time constant, the control word DCW is decreased to decrease the capacitance C.sub.N. Thus, the capacitance C.sub.N, and thereby the RC time constant .tau., is servoed to a predetermined time constant that corresponds with the desired location of a pole.
One of the problems with circuit 100 is that the voltages V.sub.N and V.sub.REF vary over process, voltage, and temperature variations. Even if the voltages V.sub.N and V.sub.REF are formed using resistors and bandgap current sources, the resistors vary considerably over process, voltage, and temperature as noted above.
Another problem with circuit 100 is that it is difficult to design a comparator that continuously compares the voltage V.sub.N on the first input to the reference voltage V.sub.REF on the second input. In classic implementations, this problem is eliminated by using strobed comparators. A strobed comparator compares the values on the first and second inputs every clock cycle to determine when the voltage V.sub.N on the first input exceeds the reference voltage V.sub.REF on the second input.
However, by performing a comparison every clock cycle, strobed comparators burn up power every cycle, resulting in increased power dissipation. In addition, if a comparison is made each clock cycle, the comparator must be reset each clock cycle. Resetting the comparator each clock cycle limits the speed of the comparator which, in turn, limits the accuracy of the calibration circuit.
Phase-locked-loops (PLL) are also utilized in some schemes to control the value of the capacitance C.sub.N of capacitor 112. Traditional PLLs, however, require some kind of analog-to-digital conversion (ADC) to provide the digital control word to capacitor 112.
Thus, there is a need for an RC calibration circuit that allows the time constant .tau.to be set to a value that is substantially equal to a predetermined time constant while consuming less power and providing greater accuracy.